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Publications by A. Pegatoquet
Using Unified Power Format Standard Concepts for Power-Aware Design and Verification of Systems-On-Chip at Transaction Level
IET Circuits, Devices and Systems
Control
Systems Engineering
Electrical
Electronic Engineering
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API for Power-Aware Application Design on Mobile Systems
LusSy: An Open Tool for the Analysis of Systems-On-A-Chip at the Transaction Level
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Power-Aware Operating Systems for Interactive Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Methodology for Power-Aware Coherent Receiver Design
Design of Area-Efficient, Low-Quiescent-Current LDOs for Chip-Level Power Management
Implementation of Unified Power Flow Controller and Verification for Transmission Capability Improvement
IEEJ Transactions on Power and Energy
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Modeling and Analysis of Power-Aware Systems
Lecture Notes in Computer Science
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The Power of Verification for Greedy Mechanism Design
Journal of Artificial Intelligence Research
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A Low Power SOC Architecture for the V2.0+EDR Bluetooth Using a Unified Verification Platform
IEICE Transactions on Information and Systems
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