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Publications by Chung-Ju Wu

Copy Propagation Optimizations for VLIW DSP Processors With Distributed Register Files

English

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Deadline-Constrained Clustered Scheduling for VLIW Architectures Using Power-Gated Register Files

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Fast 2d-DCT Implementations for VLIW Processors

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Compiler Optimizations for Adaptive EPIC Processors

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2001English

Register Coalescing Techniques for Heterogeneous Register Architecture With Copy Sifting

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Optimizing Instruction Scheduling and Register Allocation for Register-File-Connected Clustered VLIW Architectures

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DSP Processors Hit the Mainstream

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Data-Path Synthesis of VLIW Video Signal Processors

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Optimizing a Fast Stream Cipher for VLIW, SIMD, and Superscalar Processors

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Communication Optimizations for Distributed-Memory X10 Programs

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