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Publications by D.S.R.Krishna kaala
Design of Low Power Negative Pulse-Triggered Flip-Flop With Enhanced Latch
IOSR Journal of VLSI and Signal Processing
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Power Efficient Design of Semi-Dynamic Master-Slave Single-EdgeTriggered Flip-Flop
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A Novel Latch Design for Low Power Applications
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Review Paper on Power Efficient Hybrid D-Flip Flop
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Efficient Explicit Pulsed Double Edge Triggered Flip-Flop by Using Dependency on Data
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Design of Low Power Sense Amplifier Based NAND Latch Under 30nm Technology
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