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Publications by Dhasarathan S
Low Power Circuit for Brent-Kung Adder Based on Adiabatic Logic
International Journal of Advances in Signal and Image Sciences
Related publications
Adiabatic Logic Circuits for Low Power VLSI Applications
International Journal of Science and Research (IJSR)
Cascadable Adiabatic Logic Circuits for Low-Power Applications
IET Circuits, Devices and Systems
Control
Systems Engineering
Electrical
Electronic Engineering
Ultralow-Power and Secure S-Box Circuit Using FinFET Based ECRL Adiabatic Logic
Journal of Science and Technology
Low Power Adder Based ANN
International Journal of Computer Applications
Low-Power Adiabatic Computing With Improved Quasistatic Energy Recovery Logic
VLSI Design
Electronic Engineering
Computer Graphics
Hardware
Electrical
Architecture
Computer-Aided Design
Low Power Adder Based Auditory Filter Architecture
The Scientific World Journal
Biochemistry
Medicine
Genetics
Molecular Biology
Environmental Science
Low Power Wallace and Dadda Multiplier Based on CLRCL Full Adder
IJARCCE
Limited Switch Dynamic Logic Circuits for High-Speed Low-Power Circuit Design
IBM Journal of Research and Development
Computer Science
Low Power-Area Design of Full Adder Using Self Resetting Logic With GDI Technique
SSRN Electronic Journal
