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Publications by Gurindar S. Sohi
Author Retrospective for Cooperative Cache Partitioning for Chip Multiprocessors
Dynamic Dependency Analysis of Ordinary Programs
ACM SIGARCH Computer Architecture News
High-Bandwidth Address Translation for Multiple-Issue Processors
ACM SIGARCH Computer Architecture News
Understanding the Backward Slices of Performance Degrading Instructions
Multiscalar Processors
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Software-Hardware Cooperative DRAM Bank Partitioning for Chip Multiprocessors
Lecture Notes in Computer Science
Computer Science
Theoretical Computer Science
Adaptive Zone-Aware Multi-Bank on Chip Last Level L2 Cache Partitioning for Chip Multiprocessors
International Journal of Computer Applications
Optimizing Shared Cache Behavior of Chip Multiprocessors
Adaptive Mechanisms and Policies for Managing Cache Hierarchies in Chip Multiprocessors
Software Cache Coherence for Large Scale Multiprocessors
Photonic Networks-On-Chip for Future Generations of Chip Multiprocessors
IEEE Transactions on Computers
Hardware
Architecture
Mathematics
Computational Theory
Theoretical Computer Science
Software
An Advanced Compiler Framework for Non-Cache-Coherent Multiprocessors
IEEE Transactions on Parallel and Distributed Systems
Hardware
Computational Theory
Signal Processing
Architecture
Mathematics
Optimizing Array-Intensive Applications for On-Chip Multiprocessors
IEEE Transactions on Parallel and Distributed Systems
Hardware
Computational Theory
Signal Processing
Architecture
Mathematics
An Efficient Cache Design for Scalable Glueless Shared-Memory Multiprocessors