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Publications by Nayanathara K.S
Design of Low Power SAR ADC for ECG Using 45nm CMOS Technology
International Journal of VLSI Design & Communication Systems
Related publications
Optimized CMOS Design of Full Adder Using 45nm Technology
International Journal of Computer Applications
Low Power SAR-ADC in 0.18μm Mixed-Mode CMOS Process for Biomedical Applications
IOSR Journal of VLSI and Signal Processing
Techniques for Sigma Delta ADC Design Using CMOS Technology for CODEC
International Journal of Innovative Technology and Exploring Engineering
Mechanics of Materials
Electronic Engineering
Civil
Structural Engineering
Electrical
Computer Science
Design a Low Power Half-Subtractor Using .90µm CMOS Technology
IOSR journal of VLSI and Signal Processing
Design and Analysis of a Novel Ultra-Low Power SRAM Bit-Cell at 45nm CMOS Technology for Bio-Medical Implants
International Journal of Computer Applications
Design of Low Power High Performance 32 Bit Alu Using Different Adders in 45nm Technology
International Journal of Advance Engineering and Research Development
Low Power Current Mode ADC for CMOS Sensor IC
Design and Analysis of Low Power Analog to Digital Converter Using CMOS Technology
IARJSET
A 3-Bit 10-MSps Low Power CMOS Flash ADC
Communications on Applied Electronics
