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Publications by Neeraj Kr Shukla
Design and Analysis of a Novel Ultra-Low Power SRAM Bit-Cell at 45nm CMOS Technology for Bio-Medical Implants
International Journal of Computer Applications
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Design of Low Power SAR ADC for ECG Using 45nm CMOS Technology
International Journal of VLSI Design & Communication Systems
Design of Low Power High Performance 32 Bit Alu Using Different Adders in 45nm Technology
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Design and Analysis of Two Low-Power SRAM Cell Structures
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Design of Low Power SRAM Using Hierarchical Divided Bit-Line Approach in 180-Nm Technology
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Design of 8T CNTFET SRAM for Ultra-Low Power Microelectronic Applications
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Inexact-Aware Architecture Design for Ultra-Low Power Bio-Signal Analysis
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A Novel Switched Capacitor Technique for NBTI Tolerant Low Power 6t-Sram Cell Design
IOSR journal of VLSI and Signal Processing
Optimized CMOS Design of Full Adder Using 45nm Technology
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Low Power and High Speed 13T SRAM Cell With Bit-Interleaving Capability
International Journal of Computer Applications
