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Publications by P. Kaviya
Design of Low Power Sense Amplifier Based NAND Latch Under 30nm Technology
International Journal of Computer Applications
Related publications
A Novel Latch Design for Low Power Applications
International Journal of Computer Applications
Low Power Si-Based Power Amplifier for Healthcare Application
International Journal of Pharmacy and Pharmaceutical Sciences
Pharmacology
Pharmaceutical Science
Design of Low Power High Speed D-Latch Using Stacked Inverter and Sleep Transistor at 32nm CMOS Technology
International Journal of Trend in Scientific Research and Development
Design of Low Power Negative Pulse-Triggered Flip-Flop With Enhanced Latch
IOSR Journal of VLSI and Signal Processing
High Bandwidth Low Power Operational Amplifier Design and Compensation Techniques
Design of Medium Power Amplifier Using GaAs PHEMT Technology for Wireless Applications
Design of an Active Inductor Based Low Noise Amplifier Using 180nm Cmos Technology for RF Receivers
International Journal for Research in Applied Science and Engineering Technology
Low-Noise Amplifier Design
Comparative Analysis and Design of Different Type of Low Power High Speed Dynamic Double Latch Comparator Using H-Spice and CMOS Technology
International Journal for Research in Applied Science and Engineering Technology
