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Publications by Prakash Pawar

Design of Pulse Detectors and Unsigned Sequential Multiplier Using Reversible Logic

International Journal of Computer Applications
2014English

Related publications

A New Design of Multiplier Using Modified Booth Algorithm and Reversible Gate Logic

International Journal of Computer Applications Technology and Research
2013English

Design of Fast Fault Tolerant Reversible Signed Multiplier

International Journal of the Physical Sciences
2012English

Efficient Design of Reversible Sequential Circuit

IOSR Journal of Computer Engineering
2012English

Energy-Efficient Approximate Multiplier Design Using Bit Significance-Driven Logic Compression

2017English

An 180 MHz 16 Bit Multiplier Using Asynchronous Logic Design Techniques

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VHDL Design and Implementation of C.P.U by Reversible Logic Gates

International Journal of Advanced Scientific Technologies in Engineering and Management Sciences
2016English

Cross-Layer Design of Sequential Detectors in Sensor Networks

IEEE Transactions on Signal Processing
Electronic EngineeringSignal ProcessingElectrical
2006English

A Review on Multiplier Based on Reversible Logic Gate and Vedic Algorithm for Quantum Computing

International Journal of Engineering Research and
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Design of Two-Rail Checker Using a New Parity Preserving Reversible Logic Gate

International Journal of Computer Theory and Engineering
2015English

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