Amanote Research
Register
Sign In
Discover open access scientific publications
Search, annotate, share and cite publications
Publications by Prakash Pawar
Design of Pulse Detectors and Unsigned Sequential Multiplier Using Reversible Logic
International Journal of Computer Applications
Related publications
A New Design of Multiplier Using Modified Booth Algorithm and Reversible Gate Logic
International Journal of Computer Applications Technology and Research
Design of Fast Fault Tolerant Reversible Signed Multiplier
International Journal of the Physical Sciences
Efficient Design of Reversible Sequential Circuit
IOSR Journal of Computer Engineering
Energy-Efficient Approximate Multiplier Design Using Bit Significance-Driven Logic Compression
An 180 MHz 16 Bit Multiplier Using Asynchronous Logic Design Techniques
VHDL Design and Implementation of C.P.U by Reversible Logic Gates
International Journal of Advanced Scientific Technologies in Engineering and Management Sciences
Cross-Layer Design of Sequential Detectors in Sensor Networks
IEEE Transactions on Signal Processing
Electronic Engineering
Signal Processing
Electrical
A Review on Multiplier Based on Reversible Logic Gate and Vedic Algorithm for Quantum Computing
International Journal of Engineering Research and
Design of Two-Rail Checker Using a New Parity Preserving Reversible Logic Gate
International Journal of Computer Theory and Engineering