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Publications by S. Borkar
A 4-GHz 130-Nm Address Generation Unit With 32-Bit Sparse-Tree Adder Core
IEEE Journal of Solid-State Circuits
Electronic Engineering
Electrical
A Low-Leakage Dynamic Multi-Ported Register File in 0.13 Μm CMOS
Related publications
An Energy-Efficient 32-Bit Multiplier Architecture in 90-Nm CMOS
Processor Design Using 32 Bit Single Precision Floating Point Unit
International Journal of Trend in Scientific Research and Development
A 5-GHz Differential Low-Noise Amplifier With High Pin-To-Pin ESD Robustness in a 130-Nm CMOS Process
IEEE Transactions on Microwave Theory and Techniques
Electronic Engineering
Radiation
Electrical
Condensed Matter Physics
Improved Fault Tolerant Sparse KOGGE Stone ADDER
International Journal of Computer Applications
4‐bit Boolean Functions in Generation and Cryptanalysis of Secure 4‐bit Crypto S‐boxes
Security and Privacy
Delay Efficient 128-Bit Ladner-Fischer Adder
International Journal of Electronics, Communication & Instrumentation Engineering Research and Development
350 mV, 0.5 mW, 5 GHz, 130 Nm CMOS Class-C VCO Design Using Open Loop Analysis
32-Bit MIPS RISC Processor
International Journal for Research in Applied Science and Engineering Technology
A 231-MHz, 2.18-mW 32-Bit Logarithmic Arithmetic Unit for Fixed-Point 3-D Graphics System
IEEE Journal of Solid-State Circuits
Electronic Engineering
Electrical
