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Publications by Suk-Kyu Ryu
A Fast Simulation Framework for Full-Chip Thermo-Mechanical Stress and Reliability Analysis of Through-Silicon-Via Based 3D ICs
Thermal Stress Induced Delamination of Through Silicon Vias in 3-D Interconnects
Related publications
Electrical Modeling and Characterization of Through Silicon via for Three-Dimensional ICs
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Experimental Stress Characterization and Numerical Simulation for Copper Pumping Analysis of Through-Silicon Vias
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KLauS – A Charge Readout and Fast Discrimination Chip for Silicon Photomultipliers
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Analysis of Parallelization Efficiency of Coupled Thermo-Hydro-Mechanical Simulation
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3D Convolutional GAN for Fast Simulation
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X-Ray Nanodiffraction Analysis of Stress Oscillations in a W Thin Film on Through-Silicon Via
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