Structure Optimization for Timing in Nano Scale FinFET

IEICE Electronics Express - Japan
doi 10.1587/elex.12.20150297
Full Text
Abstract

Available in full text

Date
Authors
Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Related search

Strain Silicon Optimization for Memory and Logic in Nano-Scale CMOS

2007English

An Optimization Method for NBTI-aware Design of Domino Logic Circuits in Nano-Scale CMOS

IEICE Electronics Express
Electronic EngineeringCondensed Matter PhysicsOpticalElectricalMagnetic MaterialsElectronic
2011English

Impact of Defect Structure on ’Bulk’ and Nano-Scale Ferroelectrics

2011English

Optimization of FinFET-Based Gain Cells for Low Power Sub-Vt Embedded DRAMs

Journal of Low Power Electronics
Electronic EngineeringElectrical
2018English

Structure and Characteristics of Automobile Exhaust Catalysts. In View of Nano-Scale.

Materia Japan
1996English

A Structure Optimization Algorithm of Neural Networks for Large-Scale Data Sets

2014English

Wire-Demotion for Static Timing Optimization in Advanced Technology Nodes

Journal of Engineering and Applied Sciences
Engineering
2019English

Adaptive Blind Timing Recovery Methods for MSE Optimization

Eurasip Journal on Advances in Signal Processing
HardwareElectronic EngineeringSignal ProcessingElectricalArchitecture
2012English

Design Optimization and Modeling of Charge Trap Transistors (CTTs) in 14 Nm FinFET Technologies

IEEE Electron Device Letters
Electronic EngineeringOpticalElectricalMagnetic MaterialsElectronic
2019English

Amanote Research

Note-taking for researchers

Follow Amanote

© 2024 Amaplex Software S.P.R.L. All rights reserved.

Privacy PolicyRefund Policy