Amanote Research
Register
Sign In
Strain Silicon Optimization for Memory and Logic in Nano-Scale CMOS
doi 10.1109/isqed.2007.151
Full Text
Open PDF
Abstract
Available in
full text
Date
March 1, 2007
Authors
Rajani Kuchipudi
Hamid Mahmoodi
Publisher
IEEE
Related search
An Optimization Method for NBTI-aware Design of Domino Logic Circuits in Nano-Scale CMOS
IEICE Electronics Express
Electronic Engineering
Condensed Matter Physics
Optical
Electrical
Magnetic Materials
Electronic
Variability-Conscious Circuit Designs for Low-Voltage Memory-Rich Nano-Scale CMOS LSIs
Lecture Notes in Computer Science
Computer Science
Theoretical Computer Science
Structure Optimization for Timing in Nano Scale FinFET
IEICE Electronics Express
Electronic Engineering
Condensed Matter Physics
Optical
Electrical
Magnetic Materials
Electronic
A Timing Macro Model for Performance Optimization of CMOS Logic Circuits.
BTI Impact on Logical Gates in Nano-Scale CMOS Technology
Novel Low Cost, Double-And-Triple-Node-Upset-Tolerant Latch Designs for Nano-Scale CMOS
IEEE Transactions on Emerging Topics in Computing
Computer Science Applications
Information Systems
Computer Science
Human-Computer Interaction
Metrology and Characterization for Extending Silicon CMOS
AIP Conference Proceedings
Astronomy
Physics
A Notation for Designing Restoring Logic Circuitry in CMOS
Microelectronics Journal
Technology Mapping Algorithms for CMOS Dynamic Logic Circuits.
