Amanote Research

Amanote Research

    RegisterSign In

Statistical Simulation of Chip Multiprocessors Running Multi-Program Workloads

doi 10.1109/iccd.2007.4601940
Full Text
Open PDF
Abstract

Available in full text

Date

October 1, 2007

Authors
Davy GenbruggeLieven Eeckhout
Publisher

IEEE


Related search

Trace Factory: Generating Workloads for Trace-Driven Simulation of Shared-Bus Multiprocessors

IEEE Concurrency
1997English

Exploring Complex Brain-Simulation Workloads on Multi-Gpu Deployments

Transactions on Architecture and Code Optimization
HardwareInformation SystemsArchitectureSoftware
2020English

Adaptive Zone-Aware Multi-Bank on Chip Last Level L2 Cache Partitioning for Chip Multiprocessors

International Journal of Computer Applications
2010English

ILP-Based Approaches to Partitioning Recurrent Workloads Upon Heterogeneous Multiprocessors

2016English

Photonic Networks-On-Chip for Future Generations of Chip Multiprocessors

IEEE Transactions on Computers
HardwareArchitectureMathematicsComputational TheoryTheoretical Computer ScienceSoftware
2008English

Optimizing Shared Cache Behavior of Chip Multiprocessors

2009English

Optimizing Array-Intensive Applications for On-Chip Multiprocessors

IEEE Transactions on Parallel and Distributed Systems
HardwareComputational TheorySignal ProcessingArchitectureMathematics
2005English

Improving Scalability of Chip-Multiprocessors With Many HW Accelerators

English

Software-Hardware Cooperative DRAM Bank Partitioning for Chip Multiprocessors

Lecture Notes in Computer Science
Computer ScienceTheoretical Computer Science
2010English

Amanote Research

Note-taking for researchers

Follow Amanote

© 2025 Amaplex Software S.P.R.L. All rights reserved.

Privacy PolicyRefund Policy