Amanote Research
Register
Sign In
Power Reduction Through Clock Gating by Symbolic Manipulation
doi 10.1007/978-0-387-35311-1_32
Full Text
Open PDF
Abstract
Available in
full text
Date
January 1, 1997
Authors
Frans Theeuwen
Eric Seelen
Publisher
Springer US
Related search
Clock Gating and Negative Edge Triggering for Energy Recovery Clock
An Integer Programming Placement Approach to FPGA Clock Power Reduction
A Novel Sequential Circuit Optimization With Clock Gating Logic
Power Reduction in Test-Per-Scan BIST With Supply Gating and Efficient Scan Partitioning
Social Space and Symbolic Power
Sociological Theory
Sociology
Political Science
Symbolic Manipulation of Boolean Functions Using a Graphical Representation
Adhesion Forces Reduction by Oscillation and Its Application to Micro Manipulation
Power Constrained Test Scheduling Using Power Profile Manipulation
Manipulation or Education? : Symbolic Language, Belief System and the Truman Doctrine