Amanote Research

Amanote Research

    RegisterSign In

Superimposed In-Circuit Fault Mitigation for Dynamically Reconfigurable FPGAs

doi 10.1109/radecs.2017.8696242
Full Text
Open PDF
Abstract

Available in full text

Date

October 1, 2017

Authors
Alexandra KourfaliDavid Merodio CodinachsDirk Stroobandt
Publisher

IEEE


Related search

A Temporal Bipartitioning Algorithm for Dynamically Reconfigurable FPGAs

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
HardwareElectronic EngineeringElectricalArchitectureSoftware
2001English

Hardware JIT Compilation for Off-The-Shelf Dynamically Reconfigurable FPGAs

English

Hardware-Software Co-Synthesis of Low Power Real-Time Distributed Embedded Systems With Dynamically Reconfigurable FPGAs

English

Resource Management for Dynamically-Challenged Reconfigurable Systems

2007English

Aspects of Dynamically Reconfigurable Logic

1999English

MARTE Based Modeling Approach for Partial Dynamic Reconfigurable FPGAs

2008English

Dynamically Reconfigurable Distributed Database Systems.

1988English

High Level Modeling of Dynamic Reconfigurable FPGAs

International Journal of Reconfigurable Computing
HardwareArchitecture
2009English

Enhancement of Incremental Design for FPGAs Using Circuit Similarity

2011English

Amanote Research

Note-taking for researchers

Follow Amanote

© 2026 Amaplex Software S.P.R.L. All rights reserved.

Privacy PolicyRefund Policy