Amanote Research
Register
Sign In
Cost-Effective Scalable QC-LDPC Decoder Designs for Non-Volatile Memory Systems
doi 10.1109/icassp.2013.6638131
Full Text
Open PDF
Abstract
Available in
full text
Date
May 1, 2013
Authors
Ming-Han Chung
Yu-Min Lin
Cheng-Zhou Zhan
An Yeu Wu
Publisher
IEEE
Related search
A Parallel-Layered Belief-Propagation Decoder for Non-Layered LDPC Codes
Journal of Communications
Electronic Engineering
Electrical
Parallel LDPC Decoder Implementation on GPU Based on Unbalanced Memory Coalescing
Extended Barrel-Shifter for Versatile QC-LDPC Decoders
IEEE Wireless Communications Letters
Control
Systems Engineering
Electronic Engineering
Electrical
Astronomy
Physics
Design of Cost-Effective QC Procedures for Clinical-Chemistry Assays
Journal of Research of the National Bureau of Standards
A Flexible LDPC/Turbo Decoder Architecture
Journal of Signal Processing Systems
Control
Systems Engineering
Information Systems
Signal Processing
Simulation
Hardware
Architecture
Modeling
Theoretical Computer Science
LDPC Decoder Architecture for DVB-S2 and DVB-S2X Standards
Efficient DSP Implementation of an LDPC Decoder
Energy-Efficient and Cost-Effective Reliability Design in Memory Systems
LDPC Encoder and Decoder Architecture for Coding 3-Bit Message Vector
International Journal of Security and its Applications
Computer Science