Low-Power Memory Mapping Through Reducing Address Bus Activity

IEEE Transactions on Very Large Scale Integration (VLSI) Systems- United States

doi 10.1109/92.784092

Full Text

Abstract

Available in

Date

Authors

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Related search

Irredundant Address Bus Encoding for Low Power

English

Low Power Address Bus Encoding Using Loop Prediction

IEICE Electronics Express
Electronic EngineeringCondensed Matter PhysicsOpticalElectricalMagnetic MaterialsElectronic
2014English

Power-Optimal Encoding for a DRAM Address Bus

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
HardwareElectronic EngineeringElectricalArchitectureSoftware
2002English

NUMA Obliviousness Through Memory Mapping

2015English

Multithreshold Voltage Technology for Low Power Bus Architecture

IFIP Advances in Information and Communication Technology
Computer NetworksInformation SystemsManagementCommunications
2000English

Reducing Memory Space Consumption Through Dataflow Analysis

Computer Languages, Systems and Structures
Computer NetworksSoftwareCommunications
2011English

Universal Rotate Invert Bus Encoding for Low Power VLSI

International Journal of VLSI Design & Communication Systems
2012English

An Implementation of Low Latency Address-Mapping Logic for SSD Controllers

IEICE Electronics Express
Electronic EngineeringCondensed Matter PhysicsOpticalElectricalMagnetic MaterialsElectronic
2019English

Crosstalk-Noise-Aware Bus Coding With Low-Power Ground-Gated Repeaters

International Journal of Circuit Theory and Applications
Electronic EngineeringOpticalApplied MathematicsComputer Science ApplicationsElectricalMagnetic MaterialsElectronic
2017English

Amanote Research

Note-taking for researchers

Follow Amanote

© 2026 Amaplex Software S.P.R.L. All rights reserved.

Privacy PolicyRefund Policy