Low Power Address Bus Encoding Using Loop Prediction

IEICE Electronics Express- Japan

doi 10.1587/elex.11.20140379

Full Text

Abstract

Available in

Date

Authors

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Related search

Irredundant Address Bus Encoding for Low Power

English

Power-Optimal Encoding for a DRAM Address Bus

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
HardwareElectronic EngineeringElectricalArchitectureSoftware
2002English

Low-Power Memory Mapping Through Reducing Address Bus Activity

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
HardwareElectronic EngineeringElectricalArchitectureSoftware
1999English

Universal Rotate Invert Bus Encoding for Low Power VLSI

International Journal of VLSI Design & Communication Systems
2012English

Bus Encoding Architecture for Low-Power Implementation of an AMBA-based SoC Platform

IEE Proceedings - Computers and Digital Techniques
2002English

Multithreshold Voltage Technology for Low Power Bus Architecture

IFIP Advances in Information and Communication Technology
Computer NetworksInformation SystemsManagementCommunications
2000English

Low-Power FSMs in FPGA: Encoding Alternatives

Lecture Notes in Computer Science
Computer ScienceTheoretical Computer Science
2002English

Crosstalk-Noise-Aware Bus Coding With Low-Power Ground-Gated Repeaters

International Journal of Circuit Theory and Applications
Electronic EngineeringOpticalApplied MathematicsComputer Science ApplicationsElectricalMagnetic MaterialsElectronic
2017English

Low-Cost Bus Tracking System Using Area-Trace Algorithm

IOSR Journal of Computer Engineering
2014English

Amanote Research

Note-taking for researchers

Follow Amanote

© 2026 Amaplex Software S.P.R.L. All rights reserved.

Privacy PolicyRefund Policy