Amanote Research
Register
Sign In
Irredundant Address Bus Encoding for Low Power
doi 10.1109/lpe.2001.945397
Full Text
Open PDF
Abstract
Available in
full text
Date
Unknown
Authors
Y. Aghaghiri
F. Fallah
M. Pedram
Publisher
ACM
Related search
Low Power Address Bus Encoding Using Loop Prediction
IEICE Electronics Express
Electronic Engineering
Condensed Matter Physics
Optical
Electrical
Magnetic Materials
Electronic
Power-Optimal Encoding for a DRAM Address Bus
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Hardware
Electronic Engineering
Electrical
Architecture
Software
Universal Rotate Invert Bus Encoding for Low Power VLSI
International Journal of VLSI Design & Communication Systems
Low-Power Memory Mapping Through Reducing Address Bus Activity
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Hardware
Electronic Engineering
Electrical
Architecture
Software
Bus Encoding Architecture for Low-Power Implementation of an AMBA-based SoC Platform
IEE Proceedings - Computers and Digital Techniques
Multithreshold Voltage Technology for Low Power Bus Architecture
IFIP Advances in Information and Communication Technology
Computer Networks
Information Systems
Management
Communications
Low-Power FSMs in FPGA: Encoding Alternatives
Lecture Notes in Computer Science
Computer Science
Theoretical Computer Science
Crosstalk-Noise-Aware Bus Coding With Low-Power Ground-Gated Repeaters
International Journal of Circuit Theory and Applications
Electronic Engineering
Optical
Applied Mathematics
Computer Science Applications
Electrical
Magnetic Materials
Electronic
DC Bus Voltage Control for a Distributed Power System
IEEE Transactions on Power Electronics
Electronic Engineering
Electrical