Transistor Sizing of Logic Gates to Maximize Input Delay Variability

Journal of Low Power Electronics - United States
doi 10.1166/jolpe.2006.014
Full Text
Abstract

Available in full text

Date
Authors
Publisher

American Scientific Publishers

Related search

Delay Analysis of Half Subtractor Using CMOS and Pass Transistor Logic

International Journal of Computer Applications
2016English

Transistor Sizing for Radiation Hardening

English

Using Physical Logic Gates to Teach Digital Logic to Novice Computing Students

2019English

Light-Effect Transistor (LET) With Multiple Independent Gating Controls for Optical Logic Gates and Optical Amplification

Frontiers in Physics
Materials ScienceBiophysicsTheoretical ChemistryMathematical PhysicsAstronomyPhysicsPhysical
2016English

Static Induction Transistor Logic

1977English

COFFE: Fully-Automated Transistor Sizing for FPGAs

2013English

Gate Level Transistor Sizing by Nonlinear Optimization.

English

Compliance of Reversible Gates in Logic Designing

International Journal of Electrical, Electronics and Computers
2017English

Designing Faster CMOS Subthreshold Circuits Using Transistor Sizing and Paralled Transistor Stacks

English

Amanote Research

Note-taking for researchers

Follow Amanote

© 2024 Amaplex Software S.P.R.L. All rights reserved.

Privacy PolicyRefund Policy