A Systolic Array Architecture for the Discrete Sine Transform

IEEE Transactions on Signal Processing - United States
doi 10.1109/tsp.2002.801940
Full Text
Abstract

Available in full text

Date
Authors
Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Related search

A Reconfigurable Systolic Array Architecture for Multicarrier Wireless Applications

English

A Systolic Array-Based FPGA Parallel Architecture for the BLAST Algorithm

ISRN Bioinformatics
2012English

Dynamically Reconfigurable Systolic Array Accelerators: A Case Study With Extended Kalman Filter and Discrete Wavelet Transform Algorithms

IET Computers and Digital Techniques
HardwareElectronic EngineeringElectricalArchitectureSoftware
2010English

Efficient Systolic-Array Redundancy Architecture for Offline/Online Repair

Electronics (Switzerland)
ControlElectronic EngineeringSignal ProcessingComputer NetworksSystems EngineeringHardwareCommunicationsElectricalArchitecture
2020English

High Performance Systolic Array Core Architecture Design for DNA Sequencer

MATEC Web of Conferences
Materials ScienceEngineeringChemistry
2018English

Reconfigurable Discrete Wavelet Transform Architecture for Advanced Multimedia Systems

English

Memory Analysis and Architecture for Two-Dimensional Discrete Wavelet Transform

English

VLSI Architecture for Forward Discrete Wavelet Transform Based on B-Spline Factorization

Journal of VLSI signal processing systems for signal, image and video technology
2005English

A Systolic VLSI Architecture for Complex SVD

English

Amanote Research

Note-taking for researchers

Follow Amanote

© 2024 Amaplex Software S.P.R.L. All rights reserved.

Privacy PolicyRefund Policy