A Power Optimized Divide by N Prescaler Design on 50nm CMOS Process

IJARCCE
doi 10.17148/ijarcce.2017.6616
Full Text
Abstract

Available in full text

Date
Authors
Publisher

Tejass Publisheers

Related search

A Low-Power High-Speed True Single Phase Clock Divide-by-2/3 Prescaler

IEICE Electronics Express
Electronic EngineeringCondensed Matter PhysicsOpticalElectricalMagnetic MaterialsElectronic
2013English

0.3–4.4 GHz Wideband CMOS Frequency Divide-By-1.5 With Optimized CML-XOR Gate

IEICE Electronics Express
Electronic EngineeringCondensed Matter PhysicsOpticalElectricalMagnetic MaterialsElectronic
2017English

A Stacked Inverter-Based CMOS Power Amplifier in 65nm CMOS Process

2011English

Optimized CMOS Design of Full Adder Using 45nm Technology

International Journal of Computer Applications
2016English

Low Power CMOS LNA and Mixer Design

IOSR Journal of Electronics and Communication Engineering
2012English

A Power-Efficient 5.6-GHz Process-Compensated CMOS Frequency Divider

IEEE Transactions on Circuits and Systems II: Express Briefs
2007English

Design a Low Power Half-Subtractor Using .90µm CMOS Technology

IOSR journal of VLSI and Signal Processing
2013English

CMOS Low Power Cell Library for Digital Design

International Journal of VLSI Design & Communication Systems
2013English

High Frequency Power Optimized Ring Voltage Controlled Oscillator for 65nm CMOS Technology-Review

International Journal of Engineering Trends and Technology
2014English

Amanote Research

Note-taking for researchers

Follow Amanote

© 2024 Amaplex Software S.P.R.L. All rights reserved.

Privacy PolicyRefund Policy