A 20 Gb/S Injection-Locked Clock and Data Recovery Circuit

International Journal of VLSI Design & Communication Systems
doi 10.5121/vlsic.2014.5401
Full Text
Abstract

Available in full text

Date
Authors
Publisher

Academy and Industry Research Collaboration Center (AIRCC)

Related search

CMOS Building Blocks for 10+Gb/S Clock Data Recovery Circuit

English

A 25 Gb/S All-Digital Clock and Data Recovery Circuit for Burst Mode Applications in PONs

2017English

10-Gb/S CMOS Clock Recovery Cirucit Building Blocks Using Dual Substrate Technique

English

Injection-Locked Clocking: A New GHz Clock Distribution Scheme

2006English

A Fully Integrated 1.7-3.125 GBPS Clock and Data Recovery Circuit Using a Gated Frequency Detector

IEICE Transactions on Electronics
Electronic EngineeringOpticalElectricalMagnetic MaterialsElectronic
2005English

40 Gb/S All-Optical Packet Clock Recovery With Ultrafast Lock-In Time and Low Inter-Packet Guardbands

Optics Express
OpticsAtomicMolecular Physics,
2005English

A 0.18 Um CMOS Half-Rate Clock and Data Recovery Circuit With Reference-Less Dual Loop

English

10Gb/S Bang-Bang Clock and Data Recovery (CDR) for Optical Transmission Systems

Advances in Radio Science
2005English

All-Digital Clock and Data Recovery Architectures

English

Amanote Research

Note-taking for researchers

Follow Amanote

© 2024 Amaplex Software S.P.R.L. All rights reserved.

Privacy PolicyRefund Policy