A Fully Integrated 1.7-3.125 GBPS Clock and Data Recovery Circuit Using a Gated Frequency Detector
IEICE Transactions on Electronics - Japan
doi 10.1093/ietele/e88-c.8.1726
Full Text
Open PDFAbstract
Available in full text
Date
August 1, 2005
Authors
Publisher
Institute of Electronics, Information and Communications Engineers (IEICE)