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Publications by Anuj KumarShrivastava
Comparative Analysis of Low Power 10T and 14T Full Adder Using Double Gate MOSFET at 45nm Technology
International Journal of Computer Applications
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Design and Simulation of Low Power 10T Full Adder Using Cadence 16nM Technology
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Low Power Current-Mode Threshold Logic Gate Using Nano-Technology Double-Gate MOSFETs
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Design of Booth Multiplier Using Double Gate MOSFET
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Design of Low Power SAR ADC for ECG Using 45nm CMOS Technology
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Hazards and Glitch Power Reduction of CMOS Full Adder in 90nm Technology
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Low Power Wallace and Dadda Multiplier Based on CLRCL Full Adder
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