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Publications by Bhavana P.
Low Power and High Speed 13T SRAM Cell With Bit-Interleaving Capability
International Journal of Computer Applications
Related publications
Power and Area Efficient Sub-Threshold 6T SRAM With Horizontal Local Bit-Lines and Bit-Interleaving
Comparison of the Interconnect Capacitances of Various SRAM Cell Layouts to Achieve High Speed, Low Power SRAM Cells
Comparative Analysis of Various SRAM Cells With Low Power, High Read Stability and Low Area
International Journal of Engineering and Manufacturing
Design and Analysis of Two Low-Power SRAM Cell Structures
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Hardware
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Design and Analysis of a Novel Ultra-Low Power SRAM Bit-Cell at 45nm CMOS Technology for Bio-Medical Implants
International Journal of Computer Applications
Design of Low Power SRAM Using Hierarchical Divided Bit-Line Approach in 180-Nm Technology
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7T Based SRAM Topologies With Low Power and Higher SNM
International Journal of Innovative Technology and Exploring Engineering
Mechanics of Materials
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A Review on Low Power Sram
International Journal of Recent Trends in Engineering and Research
Low Power High Speed SQRT Carry Select Adder
IOSR journal of VLSI and Signal Processing
