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Publications by El-sied Hasaneen
Low Power Current-Mode Threshold Logic Gate Using Nano-Technology Double-Gate MOSFETs
The International Conference on Electrical Engineering
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Investigation of Gate-Induced Drain Leakage (GIDL) Current in Thin Body Devices: Single-Gate Ultra-Thin Body, Symmetrical Double-Gate, and Asymmetrical Double-Gate MOSFETs
Japanese Journal of Applied Physics, Part 1: Regular Papers & Short Notes
Engineering
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Double-Gate Fully-Depleted SOI Transistors for Low-Power High-Performance Nano-Scale Circuit Design
Comparative Analysis of Low Power 10T and 14T Full Adder Using Double Gate MOSFET at 45nm Technology
International Journal of Computer Applications
Comparative Study on the Structural Dependence of Logic Gate Delays in Double-Gate and Triple-Gate FinFETs
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Dual-Gate Low-Voltage Transparent Electric-Double-Layer Thin-Film Transistors With a Top Gate for Threshold Voltage Modulation
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A Low-Power Quadrature VCO Using Current-Reused Technique and Back-Gate Coupling
PIERS Online
A Two-Dimensional Analytical Model of Fully Depleted Asymmetrical Dual Material Gate Double-Gate Strained-Si MOSFETs
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Design of Low Power Novel Gate
International Journal of Advances in Signal and Image Sciences
Analysis of Double Gate Tunneling FET Characteristics for Low Power Designs Suppression
