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Publications by Francois Anceau
Synchronized Interconnected ADPLLs for Distributed Clock Generation in 65 Nm CMOS Technology
IEEE Transactions on Circuits and Systems II: Express Briefs
Electronic Engineering
Electrical
A Reconfigurable Distributed Architecture for Clock Generation in Large Many-Core SoC
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High-Voltage Circuits for Power Management on 65 Nm CMOS
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Multiplexed Oversampling Digitizer in 65 Nm CMOS for Column-Parallel CCD Readout
Characterization and Verification Environment for the RD53A Pixel Readout Chip in 65 Nm CMOS
Design of a Very Low-Power, Low-Cost 60 GHz Receiver Front-End Implemented in 65 Nm CMOS Technology
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40 Gop/S/Mm2 Fixed-Point Operators for Brain Computer Interface in 65 Nm CMOS
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Class J Power Amplifier for 5G Applications in 28 Nm CMOS FD-SOI Technology
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