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Publications by G. Miñana
Reducing Power of Functional Units in High-Performance Processors by Checking Instruction Codes and Resizing Adders
IET Computers and Digital Techniques
Hardware
Electronic Engineering
Electrical
Architecture
Software
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Trends in High-Performance Processors
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Instruction Scheduling for Instruction Level Parallel Processors
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GALS-based LPSP: Performance Analysis of a Novel Architecture for Low Power High Performance Security Processors
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Power Estimation on Functional Level for Programmable Processors
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Reducing Cache Power With Low-Cost, Multi-Bit Error-Correcting Codes
ACM SIGARCH Computer Architecture News
