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Publications by Gerd Ascheid
A 2.78 Mm2 65 Nm CMOS Gigabit MIMO Iterative Detection and Decoding Receiver
A Code-Generator Generator for Multi-Output Instructions
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Complexity Reduced MIMO Interleaved SC-FDMA Receiver With Iterative Detection
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Erratum To: Folded Down-Conversion Mixer for a 60 GHz Receiver Architecture in 65-Nm CMOS Technology
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Low-Complexity Iterative Detection and Decoding in Finite Geometry LDPC-coded MIMO Systems
Parallel Decoding for Lattice Reduction-Aided MIMO Receiver
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Design of a Very Low-Power, Low-Cost 60 GHz Receiver Front-End Implemented in 65 Nm CMOS Technology
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Iterative Sparse Channel Estimation and Decoding for Underwater MIMO-OFDM
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Detection and Iterative Decoding of a 2D Alphabetic Barcode
