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Publications by Imran Ahmed Khan

Power Efficient Design of Semi-Dynamic Master-Slave Single-EdgeTriggered Flip-Flop

International Journal on Electrical Engineering and Informatics
Engineering
2019English

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Design of Low Power Negative Pulse-Triggered Flip-Flop With Enhanced Latch

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"Flip Flop" Sandals.

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A Low Power, High Speed 18-Transitor True Single-Phase Clocking D Flip- Flop Design in 90nm Cmos Technology

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Area Efficient SR Flip-Flop Designed Using 90nm CMOS Technology

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Bilayer Defects Facilitate DPPC Flip-Flop

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