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Publications by J. Kamal Vijetha
Design and Simulation of Low Power 10T Full Adder Using Cadence 16nM Technology
International Journal for Research in Applied Science and Engineering Technology
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Comparative Analysis of Low Power 10T and 14T Full Adder Using Double Gate MOSFET at 45nm Technology
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Optimized CMOS Design of Full Adder Using 45nm Technology
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Low Power-Area Design of Full Adder Using Self Resetting Logic With GDI Technique
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Design and Implementation of Low Power High-Speed 16-Bit Arithmetic Units Using Different Multipliers in Cadence Virtuoso Using 45nm Technology
International Journal of Advance Engineering and Research Development
Hazards and Glitch Power Reduction of CMOS Full Adder in 90nm Technology
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Low Power Wallace and Dadda Multiplier Based on CLRCL Full Adder
IJARCCE
Hazards and Glitch Power Reduction of CMOS Full Adder in 90nm Technology
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Efficient Serial Multiplier Design Using Ripple Counters,Kogge-Stone Adder and Full Adder
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Design of an Efficient Current Mode Full-Adder Applying Carbon Nanotube Technology
International Journal of Modern Education and Computer Science