Amanote Research
Register
Sign In
Discover open access scientific publications
Search, annotate, share and cite publications
Publications by Jesús Camacho Villanueva
High Performance and Power Efficient On-Chip Network Designs Through Multiple Injection Ports
Related publications
A High Performance Network-On-Chip Scheme Using Lossless Data Compression
IEICE Electronics Express
Electronic Engineering
Condensed Matter Physics
Optical
Electrical
Magnetic Materials
Electronic
An Evaluation of an Integrated on-Chip/Off-Chip Network for High-Performance Reconfigurable Computing
International Journal of Reconfigurable Computing
Hardware
Architecture
Design of Adaptive Communication Channel Buffers for Low-Power Area-Efficient Network-On-Chip Architecture
Efficient Heuristic for Non-Linear Transportation Problem on the Route With Multiple Ports
Polish Maritime Research
Ocean Engineering
Mechanical Engineering
Performance Evaluation of CDMA Router for Network-On-Chip
International Journal of VLSI Design & Communication Systems
Applying Partial Power-Gating to Direction-Sliced Network-On-Chip
Journal of Electrical and Computer Engineering
Electronic Engineering
Signal Processing
Electrical
Computer Science
A System on Chip (Soc) - High-Performance Power Drive Applications - SVPWM Based Voltage Source Inverter
International Journal of Computer Applications
Thermal/Performance Trade-Off in Network-On-Chip Architectures
Hybrid Silicon-Photonic Network-On-Chip for Future Generations of High-Performance Many-Core Systems
Journal of Supercomputing
Hardware
Information Systems
Theoretical Computer Science
Architecture
Software
