Amanote Research
Register
Sign In
Discover open access scientific publications
Search, annotate, share and cite publications
Publications by K. Hakozaki
Drain Disturb Relaxation by Substrate Bias Selecting Scheme for Sector Erase Flash Memory With Conventional Single Stacked Gate Cell Structure
Related publications
New Erase Verify Scheme for Improving the Cycling Endurance of 2xnm NAND Flash Cell
RRWL: Round Robin-Based Wear Leveling Using Block Erase Table for Flash Memory
IEICE Transactions on Information and Systems
Electronic Engineering
Pattern Recognition
Hardware
Computer Vision
Electrical
Architecture
Artificial Intelligence
Software
Alternative Erase Verify: The Optimization for Longer Data Retention of NAND FLASH Memory
International Journal of Control and Automation
Control
Systems Engineering
A Novel Three-Dimensional NAND Flash Structure for Improving the Erase Performance
IEICE Electronics Express
Electronic Engineering
Condensed Matter Physics
Optical
Electrical
Magnetic Materials
Electronic
Advanced Depleted-Substrate Transistors: Single-Gate, Double-Gate and Tri-Gate
Threshold Voltage Shift in Hetero-Nanocystal Floating Gate Flash Memory
Materials Research Society Symposium - Proceedings
Mechanics of Materials
Materials Science
Condensed Matter Physics
Mechanical Engineering
An Analytic Saturation Model for Drain and Substrate Currents of Conventional and LDD MOSFETs
IEEE Transactions on Electron Devices
Electronic Engineering
Optical
Electrical
Magnetic Materials
Electronic
Enhanced Drain Current of 4h-SiC MOSFETs by Adopting a Three-Dimensional Gate Structure
IEEE Transactions on Electron Devices
Electronic Engineering
Optical
Electrical
Magnetic Materials
Electronic
Impact of Random Telegraph Noise Profiles on Drain-Current Fluctuation During Dynamic Gate Bias
IEEE Electron Device Letters
Electronic Engineering
Optical
Electrical
Magnetic Materials
Electronic
