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Publications by Olivier Billoint
Synchronized Interconnected ADPLLs for Distributed Clock Generation in 65 Nm CMOS Technology
IEEE Transactions on Circuits and Systems II: Express Briefs
Electronic Engineering
Electrical
In-Situ Fmax/Vmin Tracking for Energy Efficiency and Reliability Optimization
Related publications
High-Voltage Circuits for Power Management on 65 Nm CMOS
Advances in Radio Science
Erratum To: Folded Down-Conversion Mixer for a 60 GHz Receiver Architecture in 65-Nm CMOS Technology
Frontiers of Information Technology and Electronic Engineering
Electronic Engineering
Signal Processing
Computer Networks
Hardware
Communications
Electrical
Architecture
Multiplexed Oversampling Digitizer in 65 Nm CMOS for Column-Parallel CCD Readout
Characterization and Verification Environment for the RD53A Pixel Readout Chip in 65 Nm CMOS
Design of a Very Low-Power, Low-Cost 60 GHz Receiver Front-End Implemented in 65 Nm CMOS Technology
International Journal of Microwave and Wireless Technologies
Electronic Engineering
Electrical
40 Gop/S/Mm2 Fixed-Point Operators for Brain Computer Interface in 65 Nm CMOS
An X-Band Bi-Directional Transmit/Receive Module for a Phased Array System in 65-Nm CMOS
Sensors
Instrumentation
Information Systems
Electronic Engineering
Biochemistry
Analytical Chemistry
Molecular Physics,
Electrical
Atomic
Medicine
Optics
Class J Power Amplifier for 5G Applications in 28 Nm CMOS FD-SOI Technology
Journal of Integrated Circuits and Systems
Electronic Engineering
Electrical
A Reconfigurable Distributed Architecture for Clock Generation in Large Many-Core SoC
