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Publications by Sheenu Rana
Optimized CMOS Design of Full Adder Using 45nm Technology
International Journal of Computer Applications
Related publications
Design of Low Power SAR ADC for ECG Using 45nm CMOS Technology
International Journal of VLSI Design & Communication Systems
Comparative Analysis of Low Power 10T and 14T Full Adder Using Double Gate MOSFET at 45nm Technology
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Hazards and Glitch Power Reduction of CMOS Full Adder in 90nm Technology
CVR Journal of Science & Technology
Hazards and Glitch Power Reduction of CMOS Full Adder in 90nm Technology
CVR Journal of Science & Technology
Design and Simulation of Low Power 10T Full Adder Using Cadence 16nM Technology
International Journal for Research in Applied Science and Engineering Technology
Design and Analysis of CMOS Two Stage OP-AMP in 180nm and 45nm Technology
International Journal of Engineering Research and
Design and Analysis of Carry Look Ahead Adder Using CMOS Technique
IOSR Journal of Electronics and Communication Engineering
Efficient Serial Multiplier Design Using Ripple Counters,Kogge-Stone Adder and Full Adder
International Journal of Computer Applications
Design of an Efficient Current Mode Full-Adder Applying Carbon Nanotube Technology
International Journal of Modern Education and Computer Science
