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Publications by Suresh K. Sitaraman
Experimental Stress Characterization and Numerical Simulation for Copper Pumping Analysis of Through-Silicon Vias
IEEE Transactions on Components, Packaging and Manufacturing Technology
Electronic Engineering
Industrial
Manufacturing Engineering
Optical
Electrical
Magnetic Materials
Electronic
Related publications
On Finding a Simulation Model for Carbon Nanotubes as Through-Silicon-Vias
Electromagnetic Analysis for Optical Coherence Tomography Based Through Silicon Vias Metrology
Applied Optics
Electronic Engineering
Molecular Physics,
Engineering
Electrical
Atomic
Optics
Thermal Stress Induced Delamination of Through Silicon Vias in 3-D Interconnects
Experimental and Numerical Simulation of Stress Distribution in Landfills
Integration of Electrografted Layers for the Metallization of Deep Through Silicon Vias
Postbond Test of Through-Silicon Vias With Resistive Open Defects
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Hardware
Electronic Engineering
Electrical
Architecture
Software
Shot Peening of TRIP780 Steel: Experimental Analysis and Numerical Simulation
Journal of Materials Processing Technology
Alloys
Industrial
Metals
Simulation
Computer Science Applications
Manufacturing Engineering
Modeling
Composites
Ceramics
Numerical and Experimental Stress Analysis of a Composite Leaf Spring
International Journal of Engineering and Technology
Transfer Processes
Fluid Flow
Mechanical Engineering
Aerospace Engineering
A Fast Simulation Framework for Full-Chip Thermo-Mechanical Stress and Reliability Analysis of Through-Silicon-Via Based 3D ICs
