Amanote Research
Register
Sign In
Discover open access scientific publications
Search, annotate, share and cite publications
Publications by Yung-Cheng Ma
Deadline-Constrained Clustered Scheduling for VLIW Architectures Using Power-Gated Register Files
Transactions on Architecture and Code Optimization
Hardware
Information Systems
Architecture
Software
Related publications
Optimizing Instruction Scheduling and Register Allocation for Register-File-Connected Clustered VLIW Architectures
The Scientific World Journal
Biochemistry
Medicine
Genetics
Molecular Biology
Environmental Science
Copy Propagation Optimizations for VLIW DSP Processors With Distributed Register Files
A Robust Algorithm for Deadline Constrained Scheduling in IaaS Cloud Environment
IEICE Transactions on Information and Systems
Electronic Engineering
Pattern Recognition
Hardware
Computer Vision
Electrical
Architecture
Artificial Intelligence
Software
Power Constrained Test Scheduling Using Power Profile Manipulation
Scalable Sequence-Constrained Retention Register Minimization in Power Gating Design
Deadline Allocation in a Time-Constrained Workflow
International Journal of Cooperative Information Systems
Computer Science Applications
Information Systems
Delay-Constrained Scheduling: Power Efficiency, Filter Design, and Bounds
Application Adaptive Energy Efficient Clustered Architectures
A Logic Circuit Simulation for Finding Identical or Redundant Files Using Counter and Register
Advances in Image and Video Processing
