Amanote Research
Register
Sign In
Novel Approaches to Low Leakage and Area Efficient VLSI Design
doi 10.1109/iciev.2012.6317437
Full Text
Open PDF
Abstract
Available in
full text
Date
May 1, 2012
Authors
Tajrian Izma
Parag Barua
Md. Rejaur Rahman
Prianka Sengupta
M.S. Islam
Publisher
IEEE
Related search
Analysis of Leakage Power Reduction Techniques for Low Power VLSI Design
International Journal of Computer Applications
A VLSI Design for an Efficient Multiprocessor Cache Memory
Microelectronics Reliability
Surfaces
Electronic Engineering
Condensed Matter Physics
Electronic
Molecular Physics,
Nanoscience
Films
Optical
Electrical
Atomic
Magnetic Materials
Nanotechnology
Reliability
Safety
Coatings
Optics
Quality
Risk
VLSI Design of a Power-Efficient Object Detector Using PCANet
IEICE Electronics Express
Electronic Engineering
Condensed Matter Physics
Optical
Electrical
Magnetic Materials
Electronic
Design of a High Speed and Area Efficient Novel Adder for AES Applications
International Journal of Recent Technology and Engineering
Engineering
Management of Technology
Innovation
Compact Low-Voltage Power-Efficient Operational Amplifier Cells for VLSI
IEEE Journal of Solid-State Circuits
Electronic Engineering
Electrical
CMOS VLSI Design of Low Power Comparator Logic Circuits
Asian Journal of Scientific Research
Multidisciplinary
Focal-Plane and Multiple Chip VLSI Approaches to CNNs
Transient Time Slot (TTS) Based Run Time Leakage Reduction Method for Low Power VLSI Circuits
IOSR Journal of VLSI and Signal Processing
Efficient VLSI Fault Simulation
Computers and Mathematics with Applications
Mathematics
Computational Mathematics
Simulation
Modeling
Computational Theory
