Design and Implementation of Parallel Prefix Adders Using FPGAs

IOSR Journal of Electronics and Communication Engineering
doi 10.9790/2834-0654148
Full Text
Abstract

Available in full text

Date
Authors
Publisher

IOSR Journals

Related search

Design of Parallel Prefix Adders Using FPGAs

IOSR journal of VLSI and Signal Processing
2014English

Evaluation of High Speed and Low Memory Parallel Prefix Adders

IOSR Journal of Electrical and Electronics Engineering
2013English

A New Taxonomy for Reconfigurable Prefix Adders

2012English

Fast Modular Multiplication Using Parallel Prefix Adder

International Journal of Trend in Scientific Research and Development
2018English

Design and Performance Analysis of Various Adders and Multipliers Using GDI Technique

International Journal of VLSI Design & Communication Systems
2015English

Enhancement of Incremental Design for FPGAs Using Circuit Similarity

2011English

BulkSort: System Design and Parallel Hardware Implementation Considerations

International Journal of Advanced Computer Science and Applications
Computer Science
2019English

Approximate FPGA Implementation of CORDIC for Tactile Data Processing Using Speculative Adders

2017English

Implementation of LPM Address Generators on FPGAs

2006English

Amanote Research

Note-taking for researchers

Follow Amanote

© 2026 Amaplex Software S.P.R.L. All rights reserved.

Privacy PolicyRefund Policy