Design of Parallel Prefix Adders Using FPGAs

IOSR journal of VLSI and Signal Processing
doi 10.9790/4200-04334551
Full Text
Abstract

Available in full text

Date
Authors
Publisher

IOSR Journals

Related search

Design and Implementation of Parallel Prefix Adders Using FPGAs

IOSR Journal of Electronics and Communication Engineering
2013English

Evaluation of High Speed and Low Memory Parallel Prefix Adders

IOSR Journal of Electrical and Electronics Engineering
2013English

A New Taxonomy for Reconfigurable Prefix Adders

2012English

Fast Modular Multiplication Using Parallel Prefix Adder

International Journal of Trend in Scientific Research and Development
2018English

Enhancement of Incremental Design for FPGAs Using Circuit Similarity

2011English

Design and Performance Analysis of Various Adders and Multipliers Using GDI Technique

International Journal of VLSI Design & Communication Systems
2015English

Higher Radix Kogge-Stone Parallel Prefix Adder Architectures

English

Low Power Digital Signal Processor Architecture for Wireless Sensor Nodes by Using Parallel Prefix Technique

IOSR Journal of Electrical and Electronics Engineering
2014English

LUT Based Generalized Parallel Counters for State - Of - Art FPGAs

Electronics
Electronic EngineeringElectrical
2017English

Amanote Research

Note-taking for researchers

Follow Amanote

© 2024 Amaplex Software S.P.R.L. All rights reserved.

Privacy PolicyRefund Policy