VLSI Implementation of a 2/3 Viterbi Decoder and Noise Effects in Digital ICs

doi 10.22215/etd/2002-05057
Full Text
Abstract

Available in full text

Date

Unknown

Authors
Publisher

Carleton University

Related search

Implementation of Reduced Memory Viterbi Decoder Using Verilog HDL

IOSR Journal of Electronics and Communication Engineering
2013English

The Design of Efficient Viterbi Decoder and Realization by FPGA

Modern Applied Science
2012English

Design of Asynchronous Viterbi Decoder Using Pipeline Architecture

International Journal for Research in Applied Science and Engineering Technology
2018English

Design and Simulation of a Low Power Viterbi Decoder Using Constraint Length Nine

International Journal of Computer Applications
2013English

A Tiling-Scheme Viterbi Decoder in Software Defined Radio for GPUs

2011English

Implementation of Iterative Decoding Algorithms on Digital VLSI Platforms

English

An Efficient Low Power Viterbi Decoder Design Using T-Algorithm

International Journal of Computer Applications
2013English

Digital VLSI Implementation of Piecewise-Affine Controllers Based on Lattice Approach

IEEE Transactions on Control Systems Technology
ControlSystems EngineeringElectricalElectronic Engineering
2015English

High Speed Low-Power Viterbi Decoder Using Trellis Code Modulation

International Journal of Computing Algorithm
2016English

Amanote Research

Note-taking for researchers

Follow Amanote

© 2026 Amaplex Software S.P.R.L. All rights reserved.

Privacy PolicyRefund Policy