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Publications by Gajendra Sujediya
Design and Implementation of High Speed 16x16 CMOS Vedic Multiplier
International Journal of Electrical, Electronics and Computers
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Implementation of 24 Bit High Speed Floating Point Vedic Multiplier
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Design of an Efficient Binary Vedic Multiplier for High Speed Applications Using Vedic Mathematics With Bit Reduction Technique
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High Speed 32-Bit Vedic Multiplier for DSP Applications
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FPGA Implementation of a High Speed Multiplier Employing Carry Lookahead Adders in Reduction Phase
International Journal of Computer Applications
