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Publications by Jean-Pierre Walder
Multiplexed Oversampling Digitizer in 65 Nm CMOS for Column-Parallel CCD Readout
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Characterization and Verification Environment for the RD53A Pixel Readout Chip in 65 Nm CMOS
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Synchronized Interconnected ADPLLs for Distributed Clock Generation in 65 Nm CMOS Technology
IEEE Transactions on Circuits and Systems II: Express Briefs
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40 Gop/S/Mm2 Fixed-Point Operators for Brain Computer Interface in 65 Nm CMOS
An X-Band Bi-Directional Transmit/Receive Module for a Phased Array System in 65-Nm CMOS
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Erratum To: Folded Down-Conversion Mixer for a 60 GHz Receiver Architecture in 65-Nm CMOS Technology
Frontiers of Information Technology and Electronic Engineering
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A 40-Gb/S Quarter-Rate SerDes Transmitter and Receiver Chipset in 65-Nm CMOS
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A 2.78 Mm2 65 Nm CMOS Gigabit MIMO Iterative Detection and Decoding Receiver
A CMOS Image Sensor Using Column-Parallel Forward Noise-Canceling Circuitry
