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Publications by Linda Milor
Reliable Cache Design With Detection of Gate Oxide Breakdown Using BIST
Simulation of Lithography-Caused Gate Length and Interconnect Linewidth Variational Impact on Circuit Performance in Nanoscale Semiconductor Manufacturing
Impact of CD Control on Circuit Yield in Submicron Lithography
Related publications
Correlation Between Hot Carrier Stress, Oxide Breakdown and Gate Leakage Current for Monitoring Plasma Processing Induced Damage on Gate Oxide
Design of Cache Memory With Cache Controller for Low Power
Efficient Cache Architectures for Reliable Hybrid Voltage Operation Using EDC Codes
Soft Breakdown of Hafnium Oxynitride Gate Dielectrics
Journal of Applied Physics
Astronomy
Physics
Design Multipurpose Circuits With Minimum Garbage Outputs Using CMVMIN Gate
Chinese Journal of Engineering
Engineering
Chemical Engineering
Design of Booth Multiplier Using Double Gate MOSFET
International Journal of Computer Applications
Design and Implementation of UART With DFT-BIST for Data Communication
International Journal for Research in Applied Science and Engineering Technology
Evidence of Hole Direct Tunneling Through Ultrathin Gate Oxide Using P/Sup +/ Poly-SiGe Gate
IEEE Electron Device Letters
Electronic Engineering
Optical
Electrical
Magnetic Materials
Electronic
Energy-Efficient Cache Design Using Variable-Strength Error-Correcting Codes
ACM SIGARCH Computer Architecture News
