Amanote Research
Register
Sign In
Discover open access scientific publications
Search, annotate, share and cite publications
Publications by Michael L. Bushnell
Transistor Sizing of Logic Gates to Maximize Input Delay Variability
Journal of Low Power Electronics
Electronic Engineering
Electrical
Related publications
Delay Analysis of Half Subtractor Using CMOS and Pass Transistor Logic
International Journal of Computer Applications
Transistor Sizing for Radiation Hardening
Using Physical Logic Gates to Teach Digital Logic to Novice Computing Students
Light-Effect Transistor (LET) With Multiple Independent Gating Controls for Optical Logic Gates and Optical Amplification
Frontiers in Physics
Materials Science
Biophysics
Theoretical Chemistry
Mathematical Physics
Astronomy
Physics
Physical
Static Induction Transistor Logic
COFFE: Fully-Automated Transistor Sizing for FPGAs
Gate Level Transistor Sizing by Nonlinear Optimization.
Compliance of Reversible Gates in Logic Designing
International Journal of Electrical, Electronics and Computers
Designing Faster CMOS Subthreshold Circuits Using Transistor Sizing and Paralled Transistor Stacks
