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Publications by Nishanth S.
High Speed 32-Bit Vedic Multiplier for DSP Applications
International Journal of Computer Applications
Related publications
Design of an Efficient Binary Vedic Multiplier for High Speed Applications Using Vedic Mathematics With Bit Reduction Technique
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Implementation of 24 Bit High Speed Floating Point Vedic Multiplier
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Design and Implementation of High Speed 16x16 CMOS Vedic Multiplier
International Journal of Electrical, Electronics and Computers
Design of an Optimized High Speed Multiplier Using Vedic Mathematics
Contemporary Engineering Sciences
Materials Science
Mutagenesis
Computer Networks
Fluid Flow
Communications
Engineering
Health
Transfer Processes
Toxicology
Social Sciences
Implementation of Vedic Multiplier and Floating Point Matrix Multiplier in Image Compression Applications
International Journal of Innovative Technology and Exploring Engineering
Mechanics of Materials
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Civil
Structural Engineering
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32-Bit Cyclic Redundancy Codes for Internet Applications
An Energy-Efficient 32-Bit Multiplier Architecture in 90-Nm CMOS
Implementation of Power Efficient Vedic Multiplier
International Journal of Computer Applications
Design & Implementation of 3-Bit High Speed Flash ADC for Wireless LAN Applications
IJARCCE
