Amanote Research
Register
Sign In
Discover open access scientific publications
Search, annotate, share and cite publications
Publications by Prof. Shravan Kumar Sable
A Power Optimized Divide by N Prescaler Design on 50nm CMOS Process
IJARCCE
Related publications
A Low-Power High-Speed True Single Phase Clock Divide-by-2/3 Prescaler
IEICE Electronics Express
Electronic Engineering
Condensed Matter Physics
Optical
Electrical
Magnetic Materials
Electronic
0.3–4.4 GHz Wideband CMOS Frequency Divide-By-1.5 With Optimized CML-XOR Gate
IEICE Electronics Express
Electronic Engineering
Condensed Matter Physics
Optical
Electrical
Magnetic Materials
Electronic
A Stacked Inverter-Based CMOS Power Amplifier in 65nm CMOS Process
Optimized CMOS Design of Full Adder Using 45nm Technology
International Journal of Computer Applications
Low Power CMOS LNA and Mixer Design
IOSR Journal of Electronics and Communication Engineering
A Power-Efficient 5.6-GHz Process-Compensated CMOS Frequency Divider
IEEE Transactions on Circuits and Systems II: Express Briefs
Design a Low Power Half-Subtractor Using .90µm CMOS Technology
IOSR journal of VLSI and Signal Processing
CMOS Low Power Cell Library for Digital Design
International Journal of VLSI Design & Communication Systems
High Frequency Power Optimized Ring Voltage Controlled Oscillator for 65nm CMOS Technology-Review
International Journal of Engineering Trends and Technology
