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Publications by S. Barnola
Highly Manufacturable and Cost-Effective Single TaxC / HfxZr(1-x)O2 Gate CMOS Bulk Platform for LP Applications at the 45nm Node and Beyond
Effect of Poly/SiON Gate Stack Combined With Thin BOX and Ground Plane for Low VTH and Analog Applications of FDSOI Devices
Related publications
Novel Low Cost, Double-And-Triple-Node-Upset-Tolerant Latch Designs for Nano-Scale CMOS
IEEE Transactions on Emerging Topics in Computing
Computer Science Applications
Information Systems
Computer Science
Human-Computer Interaction
Architectures and Automation for Beyond-Cmos Technologies
Raised S/D for Advanced Planar MOSFET Devices: Challenges and Applications for the 20nm Node and Beyond
Comparative Analysis of Low Power 10T and 14T Full Adder Using Double Gate MOSFET at 45nm Technology
International Journal of Computer Applications
Optimized CMOS Design of Full Adder Using 45nm Technology
International Journal of Computer Applications
Design and Analysis of a Novel Ultra-Low Power SRAM Bit-Cell at 45nm CMOS Technology for Bio-Medical Implants
International Journal of Computer Applications
A Low-Power CMOS Wireless Acoustic Sensing Platform for Remote Surveillance Applications
Sensors
Instrumentation
Information Systems
Electronic Engineering
Biochemistry
Analytical Chemistry
Molecular Physics,
Electrical
Atomic
Medicine
Optics
Design of Low Power SAR ADC for ECG Using 45nm CMOS Technology
International Journal of VLSI Design & Communication Systems
A Cost-Effective Reconfigurable Accelerator for Platform-Based SOC Design
